Physical Memory

Complexity of modern memory is mostly due to the inherent tradeoff between size and speed

• Small memory accessed rapidly (e.g. CPU registers)
• Large memory has a high access latency (e.g. HDD)

Latency Numbers Every Programmer Should Know

Nanosecond

L1 Cache Reference: 1ns L2 Cache Reference: 4ns Mutex Lock: 17ns Main Memory Reference: 100ns

Micro Second

Compress 1kB w Zip: 2us Read 1 million Bytes sequentially from memory: 3us SSD random read: 16us Read 1 million Bytes sequentially from SSD: 49us Roundtrip in same datacentre: 500us Read 1 million bytes sequentially from disk: 825us

Milliseconds

Disk Seek: 2ms Packet RTT CA→ND : 150ms

Memory Hierarchy Latency Pyramid

• Registers
  • <1KB
  • 1 cycle
• L1 cache
  • 16KB
  • 5 cycles
• L2 cache
  • 256KB
  • 30 cycles
• DRAM
  • 1GB
  • 100 cycles
• Flash
  • >8GB
  • 1,000,000 cycles

Extra Reading:

Virtual Memory