Quartz 4

Registers

3 min read

Index: Real Time Computer Systems 3, ARM Cortex M0

Abstract:

  • Processor registers
    • The internal registers are used to store and process temporary data within the processor core;
    • All registers are inside the processor core hence can be accessed more quickly;
    • Load-store architecture
      • To process a data in the memory, they have to be loaded from the memory to a register, processed inside the processor, and then written back to the memory if needed;
      • In what cases results are not needed to be written back to memory?
  • Cortex-M0 register
    • Register bank
      • Sixteen 32-bit registers (thirteen are used for general-purpose);
    • Special registers;

Cortex M0

  • R0 – R12: general purpose registers
    • Low registers (R0 – R7) can be accessed by any instruction;
    • High registers (R8 – R12) sometimes cannot be accessed by some Thumb Instructions;
  • R13: Stack Pointer (SP)
    • Records the current address of the stack
    • Used for saving the context of a program while switching between tasks
    • Cortex-M0 has two SPs: Main SP, used in applications that require privileged access e.g. OS kernel, and exception handlers, and Process SP, used in baselevel application code (when not running an exception handler)
  • R14: Link Register (LR)
    • The LR is used to store the return address of a subroutine or a function call;
    • The program counter (PC) will load the value from LR after a function is finished;
  • Program Counter (PC)
    • Records the address of the current instruction code;
    • Automatically incremented by 4 at each operation (for 32-bit instruction code), except branching operations;
    • A branching operation, such as function calls, will change the PC to a specific address, meanwhile save the current PC to the Link Register (LR);

Calling and Returning Diagram:

Register Bank Diagram:

Extra:

Technical Information and Lookup:

  • xPSR, combined Program Status Register
    • Provides the information about program execution and the ALU flags;
      • Application PSR (APSR)
      • Interrupt PSR (IPSR)
      • Execution PSR (EPSR)
  • PRIMASK: Interrupt Mask Special Register
    • 1-bit PRIMASK
      • Set to one will block all the interrupts apart from non-maskable interrupt (NMI) and the hard fault exception;
  • CONTROL: special register
    • 1-bit stack definition
      • Set to one: use the process stack pointer (PSP);
      • Clear to zero: use the main stack pointer (MSP).
APSR:
N: negative flag
	Set to one if the result from ALU is negative; 
Z: zero flag 
	Set to one if the result from ALU is zero; 
C: carry flag 
	Set to one if an unsigned overflow occurs; 
V: overflow flag 
	Set to one if a signed overflow occurs;
IPSR:
IPSR number
	Current executing interrupt service routine number, Read Only
ESPR:
T: Thumb State
	Always one since Cortex-M0 only supports the Thumb State, Read Only

Graph View

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